The present invention relates to multi-color infrared sensing devices. More specifically, the invention relates to monolithic multi-color infrared imaging arrays based on the direct growth of infrared sensitive mercury cadmium telluride material structure on custom-fabricated read-out electronics on specially oriented silicon substrates by Molecular Beam Epitaxy (MBE).
Semiconductors are either naturally occurring or artificially synthesized materials in which the atomic arrangement gives rise to a specific atomic potential that forbids electrical carries (electrons or positive charges, known as holes) to freely move and therefore carry electrical currents. They act as insulators for as long as there is no additional energy provided to excite these carriers across the forbidden gap (called a band gap) that is generated by the atomic potential. An electrical current can be obtained by the excitation of electrons across the forbidden band. Necessary energy can be generated in different ways and of interest for radiation detection is the energy carried by the electromagnetic radiation waves. The incoming radiation has to be tuned (i.e. the radiation has to carry enough energy to be able to excite the electrons) with the band gap of the semiconductor in order to produce this excitation.
In a crystal, both short- and long-range order are important in defining single crystal structure. The atoms hold positions that can be associated with a well-defined grid (or lattice) having very small or nonexistent deviations from the grid positions through out the entire crystal. This periodicity in the atomic arrangement is of utmost importance for the electrical behavior of the crystal. A polycrystalline material has a short-range order, a specific geometrical positioning of the atoms in a lattice, but lacks long-range order. Only by performing a combination of translations and rotations can one recover the same geometrical arrangement of an initial test region. The polycrystalline material is formed by a multitude of grains consisting of individual single crystals. A long-range order means that by translating the crystal in any direction one recovers exactly the same structural arrangement of the atoms. A unit cell can be therefore defined, and the entire crystal can be regained by translations of this unit cell. An amorphous material lacks both short and long-range order, and consequently lacks any periodicity in its atomic arrangement.
FIG. 1 shows the unit cell for a cubic crystalline lattice and several crystal directions. The crystal planes are planes that contain atoms and are perpendicular to the respective direction. Shown as shaded, is the plane (100). Obviously, in the case of a cubic unit cell the chosen orientation of the reference system is arbitrary, thus the (100), (010) and (001) planes are equivalent. All the equivalent planes form a family of planes and are called by a generic name, which is one of the family member names. The atoms can occupy positions on the nodes of the grid or at intersections of principal lines within the unit cell (such as the center of lateral cubic faces or the intersection of body diagonals of the cube). The atoms can, as well, occupy positions at certain coordinates around the nodes or intersections of principal lines in what is called a basis. A cubic unit cell with atoms sitting at the nodal position as well as in the center of each cubic face is called a face centered cubic (fcc). Mercury cadmium telluride (HgCdTe or MCT) is an fcc lattice with a basis in which a secondary set of atoms is situated at xc2xc of the cubic length away from the fcc atoms in the (111) direction.
Mercury cadmium telluride is a semiconductor widely used as an infrared detector material. It consists of elements positioned in group II (Hg, Cd) in the periodic table of elements and in group VI (Te). The crystalline MCT is formed as a ternary material from a HgTe (mercury telluride) crystal lattice in which a certain percentage of Hg atoms is being replaced by Cd atoms. By varying the amounts of Cd atoms in replacement of Hg atoms, the electrical properties of the entire crystal can be tailored to suit the absorption and subsequent conversion of the incident infrared radiation into electrical current. Thus, short wavelength infrared (SWIR) MCT has a Cd percentage that allows radiation absorption of short wavelengths. Similarly, mid-wavelength (MWIR) MCT has a Cd percentage that allows radiation absorption of medium wavelengths, and long wavelength (LWIR) MCT has a Cd percentage that allows radiation absorption of long wavelengths. The flexibility of matching the electrical behavior of the crystal to certain application requirements by adjusting the composition of the crystal is known as band gap engineering, and is one of the great advantages of MCT. Several techniques are available for producing MCT and by far, MBE is the most reliable.
Molecular beam epitaxy (MBE) is a chemical vapor deposition (CVD) method in which the crystal is grown on a template (substrate) from atomic and/or molecular fluxes obtained by thermal evaporation of the charge material. The growth process occurs in an ultra-high vacuum (UHV) environment to minimize the presence of foreign atoms. Polycrystalline and/or amorphous material are loaded into crucibles and constitute the charge. During the growth the substrate is kept at a predefined temperature to ensure that sufficient energy is transferred to the surface to achieve specific reactions. The fluxes are adjusted by the temperatures at which the charge materials are kept. In this way the incoming atoms/molecules from the charges have to spend a certain residence time on the surface while traveling/diffusing around in order to find a geometrical position that minimizes the surface energy.
In order to control and to enhance the electrical properties of the materials grown by MBE one can use this method to add certain impurities (dopants) to the primary material. This added control offers a large advantage since it reduces the post growth processing along with the costs and increases the yield factor.
The substrate is of paramount importance for the MBE growth of crystalline materials. Its choice is primarily dictated by the lattice parameters that have to closely match the ones of the intended new material. Exceptions are rare and mismatches create an unwanted density of defects/dislocations.
In order to act as a template, the substrate itself should be a single crystal and one has to expose the periodic arrangement of the bulk material. Typically, the bonds between atoms are saturated (i.e. an atom/ion uses all of its available electrons for bond formation with its neighboring atoms). At the surface, the lack of periodicity in the direction perpendicular to the plane forces the atoms lying on the surface to react (use their available electrons) and bond with other elements, different than those present in the bulk of the material. These elements that are present at the surface are called contaminants. Such a surface is useless for the MBE growth of single crystalline materials.
For the growth of MCT one can use as substrate bulk cadmium zinc telluride (CdZnTe) for which lattice matching occurs at a Zn percentage close to 4%. A constant demand of larger area detectors prevents the use of CdZnTe as substrates since they are available in limited sizes only. Bulk CdZnTe is also expensive and brittle, reducing further its use in production environments. When using CdZnTe as a substrate one is limited by the current device fabrication technology.
The crystals used as substrates (Silicon, CdZnTe and others) are fabricated by cooling a melt of material (pure elements or compounds) in a way that allows crystal formation. Once crystallized, the previously formed ingot is cut into wafers with various orientations. Since the wafer is a single crystal (hence it contains a large number of unit cells, to be viewed as xe2x80x9cbricksxe2x80x9d) its surface can have various morphologies. The surface orientation of the substrate is very important since the initial nucleation process takes place on it. At this interface between the new crystal and the substrate the defects can be easily generated and they will further propagate through the entire crystal.
A major problem when growing a new crystal is twin formation. Crystal seeds that nucleate at different moments in time and at different locations are uncorrelated. For various surface orientations this correlation/uncorrelation can be beneficial (increasing the probability that only one crystalline orientation will survive throughout the growth process, generating a single crystal) or detrimental (supporting equally various orientations and ending with a polycrystalline material).
A silicon surface that has orientation (001) is almost flat (FIG. 3). Theoretically, it should be flat since integers of unit cells can be fit within the crystal. Other reasons are called upon to explain the surface morphology in this case. The surface energy is minimized by forming terraces. The terrace steps are almost +/xe2x88x921 monolayer from what is called the substrate surface. All the orientations that do not fit an integer number of the unit cell at the surface are bound to form steps, their number increasing with the wafer area. FIG. 2 shows a schematic of a (211) surface.
Mercury cadmium telluride is by far the most sensitive and commonly used material for infrared detectors. Such detectors generate a signal whose magnitude is proportional to the intensity of the incident radiation.
Every object usually has a distribution of xe2x80x98hotxe2x80x99 and xe2x80x98coldxe2x80x99 regions in it. The image generated by an array of photon detectors consists of white and black contrast corresponding to the hot and cold regions of the object or scene. An infrared imaging device consists of a plurality of photovoltaic diodes (detectors) fabricated on an infrared sensitive material (such as HgCdTe). When used for imaging, the signal generated by each diode has to be collected separately and multiplexed to re-construct an image on the video screen. The photovoltaic detector essentially consists of a junction formed by two dissimilar (p-type and n-type) conductivity regions in the infrared sensitive material as shown in FIG. 4A. The incident infrared radiation creates electron and hole pairs that are collected by the potential difference at the p-n junction leading to the xe2x80x98signalxe2x80x99. Also shown in the figure is the energy band diagram corresponding to the p-n junction formed in a heterostructure. The heterostructure means that the band gaps of the two regions (p and n) are different. The narrow band gap side of the junction is the absorber layer whose band gap is tuned to detect the particular wavelength of interest. The band gap of the top layer (p-layer in the FIG. 4B) is more than that of the n-layer. Such p-n junctions formed in a heterostructure reduce the surface-passivation related leakage currents.
Conventionally, the multiplexing electronics used for infrared detectors is fabricated separately on a silicon substrate. Indium metal bumps are then formed on each diode and the plurality of devices on the two different materials is then connected together by a xe2x80x98hybridizationxe2x80x99 process. These devices operate usually at 77K, the liquid nitrogen temperature, because of effects of thermal excitation. This thermal excitation process becomes concurrent to the radiationinduced excitations. In order to reduce it and to reduce its effects (dark current, noise) the detector operates at low temperature. When cooled to this temperature, the two different materials that together form the infrared imaging device (HgCdTe diode array and the read-out circuit) expand at different rates. The different coefficients of expansion lead to failure of the indium bump interconnection between the infrared detector and the signal processor, resulting in poor image resolution.
The increased demands on performance of silicon semiconductor devices and microcircuits have required the development of improved processing techniques. A key advance in the modern solid-state technology is clean processing in order to prevent the contamination of sensitive surfaces so that the stability and reproducibility of device characteristics are improved.
Traditionally, the Si wafers were cleaned using wet chemical etching processes, such as the RCA process (W. Kern and D.A. Puotinen, Cleaning solution based on hydrogen peroxide for use in silicon semiconductor technology, RCA Rev. 31, 187 (1970)) and the Shiraki processes (Japanese Laid-Open Publication No. Sho 63-46765) and a thermal cleaning in vacuum. For the Si wafers to be ready for epitaxial growth they have to undergo a contaminant removal step as well as a surface passivation step. The contaminant removal step assures that the Si surface is clean and free of foreign elements (contaminants).
Surface contaminants can be classified as molecular, ionic and atomic. Molecular contaminants are typically carbohydroxides and carbohydrides originating in the mechanical operations performed during the fabrication and handling of wafers. Organic solvent residues, grease or greasy films from containers are such molecular impurities held usually by weak electrostatic forces. Ionic contaminants are typically present after chemical etching, and can be physisorbed or chemisorbed onto the surface. Alkali ions are particularly harmful for epitaxial growth since they are known to give rise to different crystal defects. Atomic contaminants include metals such as gold, silver and copper. Atomic impurities, especially the heavy ions, have a detrimental effect on the overall performance of the devices.
Once the contaminants are removed from the wafers, the bare Si atoms of the surface are highly reactive. Atoms lying on the surface have electrons that do not participate in the bonding with the bulk atoms, creating so-called dangling bonds (FIG. 7 and FIG. 8). These dangling bonds represent unsaturated conditions with a high potential energy. They tend to grab and form bonds with any available atoms and therefore re-contaminate the surface.
In order to prevent the contamination of these surfaces during further processing and/or handling (like the loading into the MBE chamber) a passivation step is necessary. The passivation step consists of a controlled deposition of a thin layer of oxide that can be removed by thermal heating inside the MBE chamber before the growth of II-VI layers commences, to rereveal the dangling bonds of the surface Si atoms. More particularly, the oxide layer is thermally desorbed at temperatures above 850xc2x0 C. in an MBE growth chamber, thereby exposing a clean Si surface suitable for epitaxial growth. Importantly, the conventional approach requires thermal treatment of the Si wafer at a temperature above 850xc2x0 C. to remove the passivation layer. It is to be noted that this passivation step is for the initial growth surface (of the ROIC) that needs to be distinguished from the device passivation with CdTe as described later.
Moreover, crystal quality of HgCdTe grown on conventional CdZnTe bulk substrates or CdTe thin films is detrimentally impacted by the substrate""s surface quality. More particularly, the cleaning process results in an uneven surface due to the different etching (reaction) times of the various constituents (such as Cd vs. Te, or Cd vs. Zn). The HgCdTe crystal quality is affected by the defects that are formed at the interface during the nucleation. Moreover the contamination that is created by exposing the substrates to the environment is not entirely removed by the cleaning process. The presence of foreign atoms on the substrate creates nucleation centers for defects within the HgCdTe layers.
Read-Out Circuits (ROIC) are prone to failure at high temperatures. Consequently, applications requiring an opto-electronic device to be grown on an ROIC require that the entire process, be carried out at temperatures below the maximum sustainable temperature of ROIC. By subjecting some test ROICs to various temperatures in an MBE system and measuring the ROIC performance before and after the temperature treatments, we determined that the maximum temperature for the integrity of the components and circuits in the ROIC is about 500xc2x0 C. Consequently, conventional methods for preparing Si wafers are not acceptable because they require a thermal treatment at or above 850xc2x0 C.
A monolithic multispectral infrared detector array is provided for advanced imaging systems with capabilities to discriminate actual targets against decoys. The multispectral infrared detector simultaneously detects infrared radiation emitted by the target in more than one wavelength range. The unit cell of the integrated detector consists of two co-located detectors, each sensitive to a different infrared wavelength.
An infrared sensing device is provided which includes a plurality of infrared detectors containing planar photovoltaic diodes fabricated on a mesa-shaped II-VI semiconductor multi-layer structure produced by molecular beam epitaxy technique on a readout integrated circuit, which is pre-fabricated on a special silicon substrate. Two different designs for the monolithic multi-color infrared detector, (1) side-by-side architecture where the two rows of infrared detectors corresponding to two different response wavelengths are located side-by-side, and (2) simultaneous architecture, where the two detectors corresponding to two different response wavelengths are stacked together vertically, fabricated on the II-VI material structure grown on pre-fabricated ROIC, are provided in this invention. The infrared detectors are planar (p-HgCdTe regions are formed by arsenic implantation) in the first design and mesa (all HgCdTe layers are doped in-situ during the growth of HgCdTe layers by MBE) in the second design.
According to one aspect of the invention, the readout circuit (ROIC) that is needed for processing the signal generated by an infrared device is custom designed and fabricated in a standard semiconductor foundry. In the prior art such ROICs are fabricated on (100) oriented silicon wafer in such a way that the ROIC could be joined to the infrared device containing plurality of detectors by indium columns formed on each detector. This process of joining the infrared device and ROIC device is called hybridization. The yield in such prior art devices is poor due to the difference in the thermal expansion coefficients of the ROIC and infrared device at the operating temperature of 77K and the high-risk hybridization process itself. In this aspect of the invention, to enable defect-free II-VI semiconductors on silicon, the authors found that the ROIC needs to be fabricated on silicon substrates with one degree or the like tilted from the (100) crystal direction. This ensures twin-free growth of II-VI HgCdTe layers. Secondly, to preserve the circuits in the ROIC, a window free of any underlying circuits is provided for the subsequent growth of II-VI layers. To fabricate a plurality of infrared detectors connected to the ROIC, the signal input gates of ROIC covered with aluminum metal are provided in two rows adjacent to the growth window.
According to another aspect of the invention, a procedure to prepare the ROIC surface at or below 500xc2x0 C. is provided. The authors have found that this is the maximum temperature to which the ROIC could be subjected during the II-VI material growth. In the prior art, to grow II-VI material by MBE, the substrates need to be cleaned at or above 850xc2x0 C.
According to another aspect of this invention, the authors present the procedure to grow a multi-layer HgCdTe structure on the ROIC prepared according to the previous aspect of the invention. Due to the 19.3% lattice mismatch between the silicon and II-VI materials, it was previously thought that II-VI layers couldn""t be grown on silicon. By employing the low temperature surface preparation and growing a CdTe buffer layer, the authors have achieved single crystalline growth (the crystallinity is confirmed by the streaky pattern observed during the MBE growth) of at least one HgCdTe layer on the ROIC pre-fabricated on one-degree tilted (100) silicon substrates.
According to another aspect of the invention, the authors fabricate an infrared detector array containing two photovoltaic infrared detectors in each cell of the array formed on a mesarial like material structure that includes at least three layers of Group II-VI semiconductor material having different band gaps. Each infrared detecting cell is electronically connected to the corresponding signal input cells in the ROIC. The wider band gap layer significantly reduces the surface passivation-related leakage currents in the infrared detector.
According to yet another aspect of the invention, the signal output from each detector is conductively connected to the signal input cell of ROIC. Since the detector output and the ROIC input cells are located in two different planes with at least 15 micrometers height difference, the authors fabricate a mesa structure at the edges of the growth window. This is constructed by a special etching in bromine-methanol solution. Each detector output cell is then connected to the plurality of ROIC signal input gates by individual metal electrodes running down the low angle slope side of the mesa despite the large height difference between these two planes. Also, the detector common cell is connected to the ROIC common cell in a similar way.